fence_arch_ops_gcc_arm.hpp 2.7 KB

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  1. /*
  2. * Distributed under the Boost Software License, Version 1.0.
  3. * (See accompanying file LICENSE_1_0.txt or copy at
  4. * http://www.boost.org/LICENSE_1_0.txt)
  5. *
  6. * Copyright (c) 2020 Andrey Semashev
  7. */
  8. /*!
  9. * \file atomic/detail/fence_arch_ops_gcc_arm.hpp
  10. *
  11. * This header contains implementation of the \c fence_arch_operations struct.
  12. */
  13. #ifndef BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ARM_HPP_INCLUDED_
  14. #define BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ARM_HPP_INCLUDED_
  15. #include <boost/cstdint.hpp>
  16. #include <boost/memory_order.hpp>
  17. #include <boost/atomic/detail/config.hpp>
  18. #include <boost/atomic/detail/capabilities.hpp>
  19. #include <boost/atomic/detail/gcc_arm_asm_common.hpp>
  20. #include <boost/atomic/detail/header.hpp>
  21. #ifdef BOOST_HAS_PRAGMA_ONCE
  22. #pragma once
  23. #endif
  24. namespace boost {
  25. namespace atomics {
  26. namespace detail {
  27. //! Fence operations for legacy ARM
  28. struct fence_arch_operations_gcc_arm
  29. {
  30. static BOOST_FORCEINLINE void thread_fence(memory_order order) BOOST_NOEXCEPT
  31. {
  32. if (order != memory_order_relaxed)
  33. hardware_full_fence();
  34. }
  35. static BOOST_FORCEINLINE void signal_fence(memory_order order) BOOST_NOEXCEPT
  36. {
  37. if (order != memory_order_relaxed)
  38. __asm__ __volatile__ ("" ::: "memory");
  39. }
  40. static BOOST_FORCEINLINE void hardware_full_fence() BOOST_NOEXCEPT
  41. {
  42. // A memory barrier is effected using a "co-processor 15" instruction,
  43. // though a separate assembler mnemonic is available for it in v7.
  44. #if defined(BOOST_ATOMIC_DETAIL_ARM_HAS_DMB)
  45. // Older binutils (supposedly, older than 2.21.1) didn't support symbolic or numeric arguments of the "dmb" instruction such as "ish" or "#11".
  46. // As a workaround we have to inject encoded bytes of the instruction. There are two encodings for the instruction: ARM and Thumb. See ARM Architecture Reference Manual, A8.8.43.
  47. // Since we cannot detect binutils version at compile time, we'll have to always use this hack.
  48. __asm__ __volatile__
  49. (
  50. #if defined(__thumb2__)
  51. ".short 0xF3BF, 0x8F5B\n\t" // dmb ish
  52. #else
  53. ".word 0xF57FF05B\n\t" // dmb ish
  54. #endif
  55. :
  56. :
  57. : "memory"
  58. );
  59. #else
  60. uint32_t tmp;
  61. __asm__ __volatile__
  62. (
  63. BOOST_ATOMIC_DETAIL_ARM_ASM_START(%0)
  64. "mcr p15, 0, r0, c7, c10, 5\n\t"
  65. BOOST_ATOMIC_DETAIL_ARM_ASM_END(%0)
  66. : "=&l" (tmp)
  67. :
  68. : "memory"
  69. );
  70. #endif
  71. }
  72. };
  73. typedef fence_arch_operations_gcc_arm fence_arch_operations;
  74. } // namespace detail
  75. } // namespace atomics
  76. } // namespace boost
  77. #include <boost/atomic/detail/footer.hpp>
  78. #endif // BOOST_ATOMIC_DETAIL_FENCE_ARCH_OPS_GCC_ARM_HPP_INCLUDED_